Delay locked loop with delay control unit for noise elimination

ABSTRACT

Disclosed is a delay locked loop (DDL) for use in a semiconductor memory device, which has the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. The DDL includes a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal, a comparator for comparing the time-delayed signal from the modification block and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal, and a delay control unit for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the modification unit, if the counted value satisfies a predetermined condition.

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop having the ability of drastically eliminate noises.

DESCRIPTION OF THE PRIOR ART

[0002] In general, a delay locked loop (DLL) circuit reduces a skew between a clock signal and data or between an external clock and an internal clock, which is used in synchronizing an internal clock of a synchronous memory to an external clock without incurring any error. Specifically, a timing delay is occurred when an external clock is used at internal of system, and the delay locked loop controls the timing delay to synchronize the internal clock to the external clock.

[0003]FIG. 1 is a schematic block diagram of a conventional delay locked loop.

[0004] A clock signal Clock_1 is inputted to a controllable delay modification unit 100 which delays the inputted signal by a certain time period and produces a time-delayed signal Delayed_clock to a comparator 110. The comparator 110 compares the time-delayed signal Delayed_clock and a reference signal Clock_reference, and determines if the time delay should be increased (added) or decreased (subtracted), to produce one of an addition signal Add_delay or a subtraction signal Subtract_delay. The addition signal Add_delay or the subtraction signal Subtract-delay outputted from the comparator 110 is fed back to the controllable delay modification unit 100. Based on the addition signal or the subtraction signal, the controllable delay modification unit 100 modifies the time delay until the reference signal Clock_reference and the time-delayed signal Delayed_clock are synchronous in phase.

[0005] As mentioned above, the prior art is designed so that the comparator 110 determines if the time delay fed thereto from the controllable delay modification unit 100 should be increased or decreased and returns the result to the controllable delay modification unit 100 to thereby allow the time delay to be adjusted.

[0006] However, the prior art has a drawback that it is very sensitive to a power supply noise, random noise, radiation noise or other irregular noise. That is, the erroneous determination of the comparator 110 due to such noises causes an output signal to be fed back to the controllable delay modification unit 100 to be erroneous. As a result, the controllable delay modification unit 100 controls the time delay based on the erroneous signal, resulting in an unintended problem.

SUMMARY OF THE INVENTION

[0007] It is, therefore, a primary object of the present invention to provide a delay locked loop having the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise.

[0008] In accordance with a preferred embodiment of the present invention, there is provided a delay locked loop for use in a semiconductor memory device, which comprises: a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal; a comparator for comparing the time-delayed signal from the modification unit and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal; and a delay control unit for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the controllable delay modification unit, if the counted value is larger than a predetermined value.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

[0010]FIG. 1 shows a schematic block diagram of a conventional delay locked loop;

[0011]FIG. 2 is a schematic block diagram of a delay locked loop incorporating a delay control unit therein in accordance with preferred embodiments of the present invention;

[0012]FIG. 3 is a detailed block diagram of the delay control unit in accordance with a preferred embodiment of the present invention;

[0013]FIG. 4 is a detailed block diagram of the delay control unit in accordance with another preferred embodiment of the present invention;

[0014]FIG. 5 is a connection diagram illustrating a scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with a preferred embodiment of the present invention;

[0015]FIG. 6 is a connection diagram illustrating another scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with another preferred embodiment of the present invention; and

[0016]FIG. 7 is a block diagram of the addition/subtraction determination block implemented with a typical counter in accordance with another preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] There is shown in FIG. 2 a schematic block diagram of a delay locked loop incorporating a delay control unit therein in accordance with preferred embodiments of the present invention.

[0018] In FIG. 2, a clock signal Clock_1 is inputted to a controllable delay modification unit 200, which produces a time-delayed signal Delayed_clock to a comparator 210. The comparator 210 compares the time-delayed signal Delayed_clock from the controllable delay modification unit 200 and a reference signal Clock_reference, each being inputted thereto via terminals IN_CLOCK and REFERENCE respectively, and determinates if a time delay should be increased or decreased. The output of the comparator 210 is an addition signal Add_delay_i representing the increase of the time delay or a subtraction signal Sub_delay_i representing the decrease of the time delay, which is forwarded to a delay control unit 220.

[0019] The delay control unit 220 handles an erroneous delay determination that may be induced by noises introduced by a power supply or a system. Specifically, the delay control unit 220 controls the controllable delay modification unit 200 only if at least two consecutive determinations for the time delay satisfy a predetermined condition. Satisfying the condition, the delay control unit 220 outputs one of the addition signal Add_delay_i and the subtraction signal Sub_delay_i provided thereto from the comparator 210 to the controllable delay modification unit 200. Thus, the controllable delay modification unit 200 increases or decreases the time delay based on the signal from the delay control unit 220.

[0020]FIG. 3 is a detailed block diagram of the delay control unit in accordance with a preferred embodiment of the present invention.

[0021] The delay control unit in accordance with a preferred embodiment of the present invention includes an addition/subtraction determination block 300 and a reset signal generation block 310. The addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator 210 shown in FIG. 2 is relayed to the addition/subtraction determination block 300 which counts an input signal to produce one of signals Add_delay and Sub_delay for adjusting the time delay. Wherein, the Add_delay represents that the time delay is in need of increase and the Sub_delay represents that the time delay is in need of decrease. The signals Add_delay and the signal Sub_delay is relayed to the reset signal generation block 310, which produces a reset signal for initializing the addition/subtraction determination block 300.

[0022] The addition/subtraction determination block 300 may be implemented with a counter. Specifically, if the addition signal Add_delay_i is inputted to the addition/subtraction determination block 300, the addition/subtraction determination block 300 increases the counter by one. Similarly, if the subtraction signal Sub_delay_i is inputted, the addition/subtraction determination block 300 decreases the counter by one. Thus, the addition/subtraction determination block 300 produces the signal Add_delay if the counted value is reached to a first predetermined value, and produces the signal Sub_delay if it is reached to a second predetermined value.

[0023]FIG. 4 is a detailed block diagram of the delay control unit in accordance with another preferred embodiment of the present invention.

[0024] The delay control unit in accordance with another preferred embodiment of the present invention includes an addition/subtraction determination block 400 and a reset signal generation block 410. The addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator 210 shown in FIG. 2 is inputted to the addition/subtraction determination block 400 which counts an input signal to produce one of signals Add_delay and Sub_delay for adjusting the time delay. Wherein, the Add_delay represents that the time delay is in need of increase and the Sub_delay represents that the time delay is in need of decrease. In contrast to the delay control unit shown in FIG. 3, inputs to the reset signal generation block 410 shown in FIG. 4 are the signal Add_delay or Sub_delay from the comparator 210 and the signal Add_delay or Sub-delay from the addition/subtraction determination block 400. Based on these signals, the reset signal generation block 410 produces a reset signal for initializing the addition/subtraction determination block 400.

[0025] The addition/subtraction determination block 400 may be implemented with a counter. Specifically, if the addition signal Add_delay_i is inputted to the addition/subtraction determination block 400, the addition/subtraction determination block 400 increases the counter by one. Similarly, if the subtraction signal Sub_delay_i is inputted, the addition/subtraction determination block 400 decreases the counter by one. Thus, the addition/subtraction determination block 400 produces the signal Add_delay if the counted value is reached to a first predetermined value, and produces the signal Sub_delay if it is reached to a second predetermined value.

[0026] The input of the addition signal Add_delay_i and the subtraction signal Sub_delay_i is to allow the reset signal generation block 410 to reset the addition/subtraction determination block 400 if the addition signal followed by the subtraction signal is inputted thereto and vice-versa. Specifically, if a continuous input number of the addition signal to the reset signal generation block 410 exceeds a first predetermined number, the reset signal is produced to increase the time delay, and if a continuous input number of the subtraction signal to the reset signal generation block 410 exceeds a second predetermined number, the reset signal is produced to decrease the time delay.

[0027]FIG. 5 is a connection diagram illustrating a scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with a preferred embodiment of the present invention.

[0028] In operation, the addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator 210 shown in FIG. 2, and the reset signal from the reset signal generation block 310 or 410 are inputted to each of a multiplicity of shift registers which are connected in series. The multiplicity of the shift registers is divided into two groups 510 and 530. The one group of the shift registers 530 produces an output signal Add_delay-int and the second group of the shift registers 510 produces an output signal Sub_delay_int, according to a counted value set by the input signals Add_delay_i and Sub_delay_i. Reset for the shift registers serially connected produces an initial value 1 or 0. In FIG. 5, a plurality of shift registers each having the initial value 0 is placed in rightward and leftward of a shift register with the initial value 1. If the reset signal is inputted to the shift registers, each of the shift registers has a different initial value according to its type.

[0029] In FIG. 5, the first group of the shift registers 510 each being called a reset disable has an initial value set to be low, and a shift register 520 called a reset enable has an initial value set to be high. The output of the shift register 520 with the high state is moved rightward or leftward every occasion the addition signal Add_delay_i or Sub_delay_i is activated. Thereafter, if the shift register with the high state is placed right of the shift register 520, the signal Add_delay_int is outputted to increase the time delay. On the other hand, if the shift register with the high state is placed left of the shift register 520, the signal Sub_delay_int is outputted to decrease the time delay. Upon the input of the reset signal, the addition/subtraction determination block 300 or 400 is initialized.

[0030]FIG. 6 is a connection diagram illustrating another scheme which implements the addition/subtraction determination block through the use of bi-directional shift registers, in accordance with another preferred embodiment of the present invention.

[0031] In operation, the addition signal Add_delay_i and the subtraction signal Sub_delay_i from the comparator 210 shown in FIG. 2, and the reset signal from the reset signal generation block 410 are inputted to each of a multiplicity of shift registers which are connected in series. The multiplicity of the shift registers is divided into two groups 610 and 620. The one group of the shift registers 620 produces an output signal Add_delay_int and the second group of the shift registers 610 produces an output signal Sub_delay_int, according to a counted value set by the input signals Add_delay_i and Sub_delay_i. Reset for the shift registers serially connected produces an initial value of high or low. In FIG. 6, the multiplicity of the shift registers 620 each having the initial value of high is placed right of the second group, and the multiplicity of the shift registers 610 each having the initial value of low is placed right of the first group.

[0032] The addition/subtraction determination block shown in FIG. 5 is similar to that shown in FIG. 6 except that the first group of the shift registers 620 with an initial value of low and the second group of the shift registers 610 with an initial value of high are arranged in series without intervening any unit therebetween. That is, passing the values of low and high to the group of the shift registers placed right and left, respectively, produces the output signals Add_delay_int and Sub_delay. Accordingly, the addition/subtraction determination block shown in FIG. 6 has a simplified structure in contrast with that shown in FIG. 5.

[0033]FIG. 7 is a block diagram of the addition/subtraction determination block implemented with a typical counter in accordance with another preferred embodiment of the present invention.

[0034] Referring to FIG. 7, the addition/subtraction determination block of the present invention includes an addition delay counter 710, an addition delay decoder 730, a subtraction delay counter 720, a subtraction delay decoder 740, and a first and second OR gate 750 and 760.

[0035] The addition delay counter 710 receives the addition signal Add_delay_i from the comparator 210 shown in FIG. 2 and counts the number that the received signal is activated to produce a counted value. The addition delay decoder 730 receives the counted value from the addition delay counter 710 and determines if the counted value is reached to a first predetermined value. When reached, the addition delay decoder 730 outputs the addition signal Add_delay_int to the controllable delay modification unit 200 shown in FIG. 2. The first OR gate 750 performs an OR operation on the final addition signal Add_delay_int from the addition delay decoder 730 and the subtraction signal Sub_delay_i, to thereby produce a first reset signal for resetting the addition delay counter 710.

[0036] The subtraction delay counter 720 receives the subtraction signal Sub_delay_i from the comparator 210 shown in FIG. 2 and counts the number that the received signal is activated to produce a counted value. The subtraction delay decoder 740 receives the counted value from the subtraction delay counter 720 and determines if the counted value is reached to a second predetermined value. If the counted value is reached to the second predetermined value, the subtraction delay decoder 740 outputs the final output signal Sbu_delay_int to the controllable delay modification unit 200 shown in FIG. 2. The second OR gate 760 performs an OR operation on the subtraction signal Sub_delay_int from the subtraction delay decoder 740 and the addition signal Add_delay_i, to thereby produce a second reset signal for resetting the subtraction delay counter 720.

[0037] There are two cases to reset the addition delay counter 710 as follows: a) when the subtraction signal Sub_delay_i is applied during the consecutive incoming of the addition signal Add_delay_i, and b) when the counted value of the consecutive addition signals exceeds the first predetermined value. Similarly, there are two cases to reset the subtraction delay counter 720 as follows: a) when the addition signal Add_delay_i is applied during the consecutive incoming of the subtraction signal Sub_delay_i, and b) when the counted value of the consecutive subtraction signals exceeds the second predetermined value.

[0038] As mentioned above, the present invention employs a delay control unit having the ability to selectively perform an addition and subtraction function on a time delay based on a predetermined condition, to thereby drastically reduce or eliminate a power supply noise, random noise or other irregular noise.

[0039] Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. 

What is claimed is:
 1. A delay locked loop for use in a semiconductor memory device, which comprises: a delay means for delaying a clock signal fed thereto to produce a time-delayed signal; a comparing means for comparing the time-delayed signal from the delay means and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal; and a delay control means for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the delay means, if the counted value is larger than a predetermined value.
 2. The delay locked loop as recited in claim 1 , wherein the delay control means includes: an addition/subtraction determination means, in response to the output signal from the comparing means, for outputting a control signal for controlling the addition or the subtraction of the time delay to the delay means; and a reset signal generation means for producing a reset signal for initializing the addition/subtraction determination means if the control signal is activated.
 3. The delay locked loop as recited in claim 1 , wherein the delay control means includes: an addition/subtraction determination means, in response to the output signal from the comparing means, for outputting a control signal for controlling the addition or the subtraction of the time delay to the delay means; and a reset signal generation means for receiving the output signal from the comparing means and the control signal from the addition/subtraction determination means, and producing a reset signal for initializing the addition/subtraction determination means, if the control signal is activated or if the addition signal followed by the subtraction signal is inputted thereto and vice-versa.
 4. The delay locked loop as recited in claim 2 , wherein the addition/subtraction determination means includes: a first group of shift registers for receiving the reset signal from the reset signal generation means, thereby rendering an initial value thereof to be high; a second group of shift registers for receiving the reset signal from the reset signal generation means, thereby rendering an initial value thereof to be low; and a shift register placed between the first and the second groups, for shifting a state value of high rightward to output a first control signal for allowing the first group of the shift registers to produce the addition signal, if the addition signal is activated; and for shifting a state value of low leftward to output a second control signal for allowing the second group of the shift registers to produce the subtraction signal, if the subtraction signal is activated.
 5. The delay locked loop as recited in claim 2 , wherein the addition/subtraction determination means includes: a first group of shift registers for receiving the reset signal from the reset signal generation means, thereby rendering an initial value thereof to be high; and a second group of shift registers for receiving the reset signal from the reset signal generation means, thereby rendering an initial value thereof to be low; wherein the first group of shift registers shifts a state value of high rightward to output a first control signal for allowing the time delay to be increased, if the addition signal is activated; and the second of shift registers shifts a state value of low leftward to output a second control signal for allowing the time delay to be decreased, if the subtraction signal is activated.
 6. The delay locked loop as recited in claim 1 , wherein the delay control means includes: an addition delay counter for receiving the addition signal from the comparing means, and counts the number that the received signal is activated to produce a first counted value; an addition delay decoder for receiving the counted value from the addition delay counter, determining if the counted value is reached to a first predetermined value, and outputting a first control signal for allowing the time delay to be increased, when reached; a first reset means for performing a combination operation on the first control signal and the subtraction signal, to thereby produce a first reset signal for resetting the addition delay counter; a subtraction delay counter for receiving the subtraction signal from the comparing means, and counts the number that the received signal is activated to produce a second counted value; a subtraction delay decoder for receiving the counted value from the subtraction delay counter, determining if the counted value is reached to a second predetermined value, and outputting a second control signal for allowing the time delay to be decreased, when reached; and a second reset means for performing a combination operation on the second control signal and the addition signal, to thereby produce a second reset signal for resetting the subtraction delay counter.
 7. The delay locked loop as recited in claim 6 , wherein the first and second reset means include an OR gate, respectively. 